The present invention relates to differential transmission circuits which are used in large-capacity MOS integrated circuits, such as DRAM (dynamic random-access memory) and SRAM (static random-access memory), so as to differentially transmit data.
In recent years, there has been a great demand for a differential transmission circuit which performs higher-speed data transmission in response to the increasing operating speed of a MOS integrated circuit.
FIG. 1 is a circuit diagram of a conventional differential transmission circuit, which shows a ground terminal 0, a power supply terminal 1, complementary input data lines 71 and 72, complementary internal data lines 73 and 74, complementary output data lines 75 and 76, n-channel MOS transistors (hereinafter referred to as NMOS) 77 and 78 for receiving data from the input data lines 71 and 72 at their gates, p-channel MOS transistors (hereinafter referred to as PMOS) 79 and 80 for latching data from the internal data lines 73 and 74, an NMOS 81 interposed between the sources of the NMOSs 77 and 78 and the ground terminal 0, NMOSs 82 and 83 for receiving data from the internal data lines 73 and 74 at their gates, PMOSs 84 and 85 for latching data from the output data lines 75 and 76, an NMOS 86 interposed between the sources of the NMOSs 82 and 83 and the ground terminal 0, and first, second, and third precharge circuits 87, 88, and 89 for precharging their respective data lines.
The operation of the differential transmission circuit thus constituted will be described with reference to FIGS. 2(a) to 2(e). Initially, before input data (potential difference) is applied to the input data lines 71 and 72, the data lines are precharged (equalized) by the three precharge circuits 87, 88, and 89 so that each of their voltages reaches the value which turns the NMOSs 77, 78, 82, and 83 ON. When the application of input data to the gates of the NMOSs 77 and 78 is initiated, the NMOSs 81 and 86 are switched from the OFF state to the ON state by clock signals, which activates a first differential amplifying circuit composed of four MOSs 77, 78, 79, and 80 and a second differential amplifying circuit composed of four MOSs 82, 83, 84, and 85, so that the data is transmitted from the input data lines 71 and 72 to the internal data lines 73 and 74, and then from the internal data lines 73 and 74 to the output data lines 75 and 76. In this case, since the NMOSs 77, 78, 82, and 83 are already in the ON state in initiating the transmitting operation, output data can be obtained immediately on the application of clock signals to the NMOSs 81 and 86. Moreover, the NMOSs 77 and 78 for receiving input data at their gates have great current-driving abilities. Such a differential transmission circuit is disclosed in, for example, K. Sasaki et al., "A 9-ns 1-Mbit CMOS SRAM", Journal of Silid-State Circuits, Vol. 24, No. 5, Oct. 1989, pp. 1219-1225.
With the structure mentioned above, however, timing margins should be considered in timing the application of clock signals, for malfunction such as amplifying and transmitting of wrong data may occur if the application of clock signals to the gates of the NMOSs 81 and 86 is timed earlier than the supply of input data to the gates of the NMOS 77 and 78. Consequently, the data transmission speed is determined by the timing of applying clock signals, which makes it difficult for the conventional differential transmission circuit to perform faster data transmission.
Moreover, since the voltage at each of the data lines is set to a value at which the NMOSs 77, 78, 82, and 83 are turned ON during the precharge period, current is allowed to flow from the power supply terminal 1 to the ground terminal 0, which undesirably increases consumed current of the circuit. Furthermore, the current is also allowed to flow from the power supply terminal 1 to the ground terminal 0 unless a controlling peration is performed as follows. That is, precharging is initiated after clock signals are switched OFF and, after precharging is completed, clock signals are inputted to turn the NMOSs 81 and 86 ON. Such a controlling operation inevitably delays the timing of turning NMOSs 81 and 86 ON with clock signals, which prevents higher-speed data transmission.